SM470R1B1M-HT Datasheet, PDF (13/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
www.ti.com
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
Table 4. Terminal Functions
TERMINAL
NAME
HET[0]
HET[1]
HET[2]
HET[3]
HET[4]
HET[5]
HET[6]
HET[7]
HET[8]
HET[18]
HET[20]
HET[22]
CAN1HRX
CAN1HTX
CAN2HRX
CAN2HTX
GIOA[0]/INT[0]
GIOA[1]/INT[1]/ECLK
GIOA[2]/INT[2]
GIOA[3]/INT[3]
GIOA[4]/INT[4]
GIOA[5]/INT[5]
GIOA[6]/INT[6]
GIOA[7]/INT[7]
GIOB[0]/EBDMAREQ0
GIOC[0]/EBOE
GIOC[1]/EBWR[0]
GIOC[2]/EBWR[1]
GIOC[3]/EBCS[5]
GIOC[4]/EBCS[6]
PAD
NO.
76
75
74
69
68
66
9
11
13
16
19
20
86
87
57
58
144
140
138
137
130
101
81
82
46
139
131
129
123
122
HFQ/
HKP
PIN
NO. ⁽⁴⁾
42
NC
41
38
37
36
6
NC
7
NC
NC
NC
49
50
29
30
83
80
79
78
73
58
46
47
NC
NC
NC
NC
NC
NC
TYPE ^{(1) (2)}
CURRENT
OUTPUT
INTERNAL
PULLUP/
PULLDOWN ⁽³⁾
DESCRIPTION
HIGH-END TIMER (HET)
3.3 V
2 mA -z
IPD (20 µA)
HIGH-END CAN CONTROLLER (HECC)
5-V tolerant
4 mA
3.3 V
2 mA -z
IPU (20 µA)
5-V tolerant
4 mA
3.3 V
2 mA -z
IPU (20 µA)
GENERAL-PURPOSE I/O (GIO)
Timer input capture or output compare. The
HET[8:0,18,20,22] applicable pins can be
programmed as general-purpose
input/output (GIO) pins. All are high-
resolution pins.
The high-resolution (HR) SHARE feature
allows even HR pins to share the next higher
odd HR pin structures. This HR sharing is
independent of whether or not the odd pin is
available externally. If an odd pin is available
externally and shared, then the odd pin can
only be used as a general-purpose I/O. For
more information on HR SHARE, see the
TMS470R1x High-End Timer (HET)
Reference Guide (literature number
SPNU199).
HECC1 receive pin or GIO pin
HECC1 transmit pin or GIO pin
HECC2 receive pin or GIO pin
HECC2 transmit pin or GIO pin
5-V tolerant
4 mA
General-purpose input/output pins.
GIOA[7:0]/INT[7:0] are interrupt-capable
pins.
GIOA[1]/INT[1]/ECLK pin is multiplexed with
the external clock-out function of the
external clock prescale (ECP) module.
3.3 V
2 mA -z
IPD (20 µA)
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOF[7:0], GIOG[7:0], and GIOH[5,0] are
multiplexed with the expansion bus module.
See Table 9.
(1) PWR = power, GND = ground, REF = reference voltage, NC = no connect
(2) All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.
(3) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
(4) Any pins marked as NC are physically connected to ground internal to the package. Care must be used to keep these pins in a high
impedance input state.
Copyright © 2009–2012, Texas Instruments Incorporated
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