SM470R1B1M-HT Datasheet, PDF (51/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

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SM470R1B1M-HT
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
SPInCLK
(clock polarity = 0)
SPInCLK
(clock polarity = 1)
SPInSOMI
1
2
3
4
5₅
SPISOMI Data Is Valid
6
SPInSIMO
7
SPISIMO Data
Must Be Valid
Figure 17. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
SPIn Slave Mode External Timing Parameters⁽¹⁾
(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)^{(2) (3) (4) (5)} (see Figure 18)
NO.
1 t_c(SPC)S
2 ^{(7) tw(SPCH)S}
t_w(SPCL)S
3 ^{(7) tw(SPCL)S}
t_w(SPCH)S
4 ⁽⁷⁾
t_{v(SOMI-SPCH)S}
t_{v(SOMI-SPCL)S}
Cycle time, SPInCLK⁽⁶⁾
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
Valid time, SPInCLK low after SPInSOMI data valid
(clock polarity = 1)
MIN
100
0.5t_c(SPC)S – 0.25t_c(ICLK)
0.5t_c(SPC)S – 0.25t_c(ICLK)
0.5t_c(SPC)S – 0.25t_c(ICLK)
0.5t_c(SPC)S – 0.25t_c(ICLK)
MAX
UNIT
256t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S + 0.25t_c(ICLK)
0.5t_c(SPC)S – 6 – t_r
0.5t_c(SPC)S – 6 – t_f
t_{v(SPCH-SOMI)S}
5 ⁽⁷⁾
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5t_c(SPC)S – 6 – t_r
ns
t_{v(SPCL-SOMI)S}
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
0.5t_c(SPC)S – 6 – t_f
6 ⁽⁷⁾
t_{su(SIMO-SPCH)}S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 0)
6
t_{su(SIMO-SPCL)}S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 1)
6
t_{v(SPCH-SIMO)S}
7 ⁽⁷⁾
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
t_{v(SPCL-SIMO)S}
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
6
(1) Not production tested.
(2) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
(3) If the SPI is in slave mode, the following must be true: t_c(SPC) ≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].
(4) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(5) t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
(6) When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t _c(SPC)S ≥ (PS +1)t_c(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t_c(SPC)S = 2t _c(ICLK) ≥ 100 ns.
(7) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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