SM470R1B1M-HT Datasheet, PDF (21/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
www.ti.com
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
F05 Flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a 32-
bit-wide data bus interface. The F05 flash has an external state machine for programming and erase functions.
See the Flash read and Flash program and erase sections.
flash protection keys
The B1M device provides flash protection keys. These four 32-bit protection keys prevent
program/erase/compaction operations from occurring until after the four protection keys have been matched by
the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the B1M are
located in the last 4 words of the first 64K sector.
flash read
The B1M flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE
The flash external pump voltage (V_CCP) is required for all operations (program, erase, and
read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a system
clock frequency of 30 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states
when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In
other words, the B1M device powers up and comes out of reset in non-pipeline mode.
Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will override pipeline
mode.
Copyright © 2009–2012, Texas Instruments Incorporated
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