SM470R1B1M-HT Datasheet, PDF (53/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
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SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
SCIn ISOSYNCHRONOUS MODE TIMINGS - INTERNAL CLOCK
Timing Requirements for Internal Clock SCIn Isosynchronous Mode^{(1)(2) (3) (4)}
(see Figure 19)
(BAUD + 1)
IS EVEN OR BAUD = 0
(BAUD + 1)
IS ODD AND BAUD ≠ 0
MIN
MAX
MIN
MAX
t_c(SCC)
Cycle time,
SCInCLK
2t_c(ICLK)
2²⁴ t_c(ICLK)
3t_c(ICLK)
(2²⁴ – 1) t_c(ICLK)
t_w(SCCL)
Pulse duration,
SCInCLK low
0.5t_c(SCC) – t_f 0.5t_c(SCC) + 5 0.5t_c(SCC) + 0.5t_c(ICLK) – t_f
0.5t_c(SCC) + 0.5t_c(ICLK)
t_w(SCCH)
Pulse duration,
SCInCLK high
0.5t_c(SCC) – t_r 0.5t_c(SCC) + 5 0.5t_c(SCC) – 0.5t_c(ICLK) – t_r
0.5t_c(SCC) – 0.5t_c(ICLK)
Delay time,
t_d(SCCH-TXV) SCInCLK high to
10
10
SCInTX valid
t_v(TX)
Valid time,
SCInTX data after
SCInCLK low
t_c(SCC) – 10
t_c(SCC) – 10
t_su(RX-SCCL)
Setup time,
SCInRX before
SCInCLK low
t_c(ICLK) + t_f + 20
t_c(ICLK) + t_f + 20
t_v(SCCL-RX)
Valid time,
SCInRX data
after SCInCLK
low
–t_c(ICLK) + t_f + 20
–t_c(ICLK) + t_f + 20
(1) Not production tested.
(2) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
(3) t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
(4) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
UNIT
ns
ns
ns
ns
ns
ns
ns
t_c(SCC)
t_w(SCCL)
t_w(SCCH)
SCICLK
SCITX
SCIRX
t_{d(SCCHĆTXV)}
t_v(TX)
Data Valid
t_{su(RXĆSCCL)}
Data Valid
t_{v(SCCLĆRX)}
B. Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 19. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
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