SM470R1B1M-HT Datasheet, PDF (48/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
SPIn MASTER MODE TIMING PARAMETERS
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SPIn Master Mode External Timing Parameters
(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)^{(1)(2) (3) (4)} (see Figure 15)
NO.
1 t_c(SPC)M
Cycle time, SPInCLK⁽⁵⁾
2 ⁽⁶⁾
t_w(SPCH)M
t_w(SPCL)M
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
3 ⁽⁶⁾
t_w(SPCL)M
t_w(SPCH)M
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
4^{(6) td(SPCH-SIMO)M Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)}
t_{d(SPCL-SIMO)M} Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)
5 ⁽⁶⁾
t_{v(SPCL-SIMO)M}
t_{v(SPCH-SIMO)M}
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
6^{(6) tsu(SOMI-SPCL)M Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)}
t_{su(SOMI-SPCH)M} Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)
7 ⁽⁶⁾
t_{v(SPCL-SOMI)M}
t_{v(SPCH-SOMI)M}
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
MIN
100
0.5t_c(SPC)M – t_r
0.5t_c(SPC)M – t_f
0.5t_c(SPC)M – t_f
0.5t_c(SPC)M – t_r
t_c(SPC)M – 5 – t_f
t_c(SPC)M – 5 – t_r
6
6
4
4
MAX
UNIT
256t_c(ICLK)
0.5t_c(SPC)M + 5
0.5t_c(SPC)M + 5
0.5t_c(SPC)M + 5
0.5t_c(SPC)M + 5
10
10
ns
(1) Not production tested.
(2) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(3) t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
(4) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(5) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t _c(SPC)M ≥(PS +1)t_c(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: t_c(SPC)M = 2t _c(ICLK) ≥ 100 ns.
(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
SPInSOMI
7
Master In Data
Must Be Valid
Figure 15. SPIn Master Mode External Timing (CLOCK PHASE = 0)
48
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