SM470R1B1M-HT Datasheet, PDF (43/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
www.ti.com
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
Switching Characteristics over Recommended Operating Conditions for External Clocks^{(1)(2) (3)}
(4)
(see Figure 9 and Figure 10)
PARAMETER
t_w(COL)
Pulse duration, CLKOUT low
t_w(COH)
Pulse duration, CLKOUT high
t_w(EOL)
Pulse duration, ECLK low
t_w(EOH)
Pulse duration, ECLK high
TEST CONDITIONS
SYSCLK or MCLK⁽⁵⁾
ICLK: X is even or 1⁽⁶⁾
ICLK: X is odd and not 1⁽⁶⁾
SYSCLK or MCLK⁽⁵⁾
ICLK: X is even or 1⁽⁶⁾
ICLK: X is odd and not 1⁽⁶⁾
N is even and X is even or odd
N is odd and X is even
N is odd and X is odd and not 1
N is even and X is even or odd
N is odd and X is even
N is odd and X is odd and not 1
MIN
0.5t_c(SYS) – t_f
0.5t_c(ICLK) – t_f
0.5t_c(ICLK) + 0.5t_c(SYS) – t_f
0.5t_c(SYS) – t_r
0.5t_c(ICLK) – t_r
0.5t_c(ICLK) – 0.5t_c(SYS) – t_r
0.5t_c(ECLK) – t_f
0.5t_c(ECLK) – t_f
0.5t_c(ECLK) + 0.5t_c(SYS) – t_f
0.5t_c(ECLK) – t_r
0.5t_c(ECLK) – t_r
0.5t_c(ECLK) – 0.5t_c(SYS) – t_r
MAX UNIT
ns
ns
ns
ns
(1) Not production tested.
(2) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
(3) N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(4) CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
(5) Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
(6) Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
CLKOUT
t_w(COH)
t_w(COL)
Figure 9. CLKOUT Timing Diagram
t_w(EOH)
ECLK
t_w(EOL)
Figure 10. ECLK Timing Diagram
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