SM470R1B1M-HT Datasheet, PDF (42/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
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ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled⁽¹⁾
MIN
TYP
MAX UNIT
f_(OSC)
t_c(OSC)
t_w(OSCIL)
t_w(OSCIH)
f_(OSCRST)
Input clock frequency
Cycle time, OSCIN
Pulse duration, OSCIN low
Pulse duration, OSCIN high
OSC FAIL frequency⁽²⁾
4
10 MHz
100
ns
15
ns
15
ns
53
kHz
(1) Not production tested.
(2) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
Switching Characteristics over Recommended Operating Conditions for Clocks^{(1)(2) (3) (4)}
f_(SYS)
PARAMETER
System clock frequency⁽⁶⁾
TEST CONDITIONS⁽⁵⁾
Pipeline mode enabled
Pipeline mode disabled
MIN
MAX
60 ⁽⁷⁾
24
f_(CONFIG)
System clock frequency - flash config mode
24
f_(ICLK)
Interface clock frequency
Pipeline mode enabled
30
Pipeline mode disabled
24
Pipeline mode enabled
30
f_(ECLK)
External clock output frequency for ECP module
Pipeline mode disabled
24
t_c(SYS)
Cycle time, system clock
Pipeline mode enabled
16.7
Pipeline mode disabled
41.6
t_c(CONFIG)
t_c(ICLK)
Cycle time, system clock - flash config mode
Cycle time, interface clock
41.6
Pipeline mode enabled
33.3
Pipeline mode disabled
41.6
t_c(ECLK)
Cycle time, ECP module external clock output
Pipeline mode enabled
33.3
Pipeline mode disabled
41.6
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
(1) Not production tested.
(2) f_(SYS) = M × f_(OSC)/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f_(SYS) = f_(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f_(ICLK) = f_(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
(3) f_(ECLK) = f_(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(4) Only ZPLL mode is available. FM mode must not be turned on.
(5) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
(6) Flash Vread must be set to 5 V to achieve maximum system clock frequency.
(7) Operating V_CC range for this system clock frequency is 1.81 to 2.05 V.
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