SM470R1B1M-HT Datasheet, PDF (55/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
www.ti.com
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
I2C TIMING
I2C Signals (SDA and SCL) Switching Characteristics⁽⁵⁾⁽⁶⁾ Assumes testing over recommended operating
conditions.
I2C Signals (SDA and SCL) Switching Characteristics⁽¹⁾⁽²⁾
PARAMETER
STANDARD MODE
MIN
MAX
FAST MODE
UNIT
MIN
MAX
t_c(I2CCLK)
t_c(SCL)
t_{su(SCLH-SDAL)}
Cycle time, I2C module clock
Cycle time, SCL
Setup time, SCL high before SDA low (for a repeated START
condition)
75
150
10
4.7
75
150 ns
2.5
µs
0.6
µs
t_h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START
condition)
4
0.6
µs
t_w(SCLL)
t_w(SCLH)
t_su(SDA-SCLH)
t_h(SDA-SCLL)
t_w(SDAH)
t_r(SCL)
t_r(SDA)
t_f(SCL)
t_f(SDA)
t_{su(SCLH-SDAH)}
t_w(SP)
C_b ⁽⁴⁾
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
For I2C bus devices
Pulse duration, SDA high between STOP and START conditions
Rise time, SCL
Rise time, SDA
Fall time, SCL
Fall time, SDA
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4.7
1.3
µs
4
0.6
µs
250
100
ns
0
3.45 ⁽³⁾
0
0.9
µs
4.7
1.3
µs
1000 20+0.1C_b ⁽⁴⁾ 300
ns
1000 20+0.1C_b ⁽⁴⁾ 300
ns
300
20+0.1C_b ⁽⁴⁾ 300
ns
300
20+0.1C_b ⁽⁴⁾ 300
ns
4.0
0.6
µs
0
50
ns
400
400 pF
(5) Not production tested.
(6) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(1) Not production tested.
(2) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(3) The maximum t_h(SDA-SCLL) for I2C bus devices needs to be met only if the device does not stretch the low period (t_w(SCLL)) of the SCL
signal.
(4) C _b = The total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
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