SM470R1B1M-HT Datasheet, PDF (54/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLER

SM470R1B1M-HT
SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012
SCIn ISOSYNCHRONOUS MODE TIMINGS - EXTERNAL CLOCK
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Timing Requirements for External Clock SCIn Isosynchronous Mode^{(1)(2) (3)}
(see Figure 20)
t_c(SCC)
t_w(SCCH)
t_w(SCCL)
t_d(SCCH-TXV)
t_v(TX)
t_su(RX-SCCL)
t_v(SCCL-RX)
Cycle time, SCInCLK⁽⁴⁾
Pulse duration, SCInCLK high
Pulse duration, SCInCLK low
Delay time, SCInCLK high to SCInTX valid
Valid time, SCInTX data after SCInCLK low
Setup time, SCInRX before SCInCLK low
Valid time, SCInRX data after SCInCLK low
MIN
8t_c(ICLK)
0.5t_c(SCC) – 0.25t_c(ICLK)
0.5t_c(SCC) – 0.25t_c(ICLK)
2t_c(SCC) – 10
0
2t_c(ICLK) + 10
MAX
0.5t_c(SCC) + 0.25t_c(ICLK)
0.5t_c(SCC) + 0.25t_c(ICLK)
2t_c(ICLK) + 12 + t _r
(1) Not production tested.
(2) t_c(ICLK) = interface clock cycle time = 1/f_(ICLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When driving an external SCInCLK, the following must be true: t_c(SCC) ≥ 8t_c(ICLK).
UNIT
ns
ns
ns
ns
ns
ns
ns
t_c(SCC)
t_w(SCCL)
t_w(SCCH)
SCICLK
SCITX
SCIRX
t_{d(SCCHĆTXV)}
t_v(TX)
Data Valid
t_{su(RXĆSCCL)}
Data Valid
t_{v(SCCLĆRX)}
C. Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 20. SCIn Isosynchronous Mode Timing Diagram for External Clock
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