DS90UB924-Q1 Datasheet, PDF (56/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

DS90UB924-Q1
SNLS512 – APRIL 2016
www.ti.com
Layout Guidelines (continued)
Table 11. No Pullback WQFN Stencil Aperture Summary
DEVICE
PIN MKT Dwg
COUNT
PCB I/O
Pad Size
(mm)
PCB
PITCH
(mm)
PCB DAP
SIZE (mm)
STENCIL I/O
APERTURE
(mm)
STENCIL DAP
Aperture (mm)
DS90UB924-Q1 48 RHS0048A 0.25 x 0.4
0.5
5.1 x 5.1
0.25 x 0.6
5.1 x 5.1
NUMBER of
DAP
APERTURE
OPENINGS
1
Figure 42 shows the PCB layout example derived from the layout design of the DS90UB924QEVM evaluation
board. The graphic and layout description are used to determine both proper routing and proper solder
techniques when designing the Serializer board.
10.1.1 CML Interconnect Guidelines
See Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and
Application Note 905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for
full details.
• Use 100 Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187).
56
Submit Documentation Feedback
Product Folder Links: DS90UB924-Q1
Copyright © 2016, Texas Instruments Incorporated