DS90UB924-Q1 Datasheet, PDF (45/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

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DS90UB924-Q1
SNLS512 – APRIL 2016
Register Maps (continued)
Table 8. Serial Control Bus Registers ^{(1) (2)} (continued)
ADD
(dec)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
41
0x29 FRC Control
7
RW
0x00
Timing
Mode
Select
Select Display Timing Mode
0: DE only Mode (default)
1: Sync Mode (VS,HS)
6
RW
HS Polarity Horizontal Sync Polarity Select
0: Active High (default)
1: Active Low
5
RW
VS Polarity Vertical Sync Polarity Select
0: Active High (default)
1: Active Low
4
RW
DE Polarity Data Enable Sync Polarity Select
0: Active High (default)
1: Active Low
3
RW
FRC2
Enable
FRC2 Enable
0: FRC2 disable (default)
1: FRC2 enable
2
RW
FRC1
Enable
FRC1 Enable
0: FRC1 disable (default)
1: FRC1 enable
1
RW
Hi-FRC2
Enable
Hi-FRC2 Enable
0: Hi-FRC2 enable (default)
1: Hi-FRC2 disable
0
RW
Hi-FRC1
Enable
Hi-FRC1 Enable
0: Hi-FRC1 enable (default)
1: Hi-FRC1 disable
43
0x2B I2S Control
7
RW
0x00 I2S PLL
Override I2S PLL
Override 0: PLL override disabled (default)
1: PLL override enabled
6
RW
I2S PLL
Enable
Enable I2S PLL
0: I2S PLL is on for I2S data jitter cleaning (default)
1: I2S PLL is off. No jitter cleaning
5:1
Reserved
0
RW
I2S Clock
Edge
I2S Clock Edge Select
0: I2S Data is strobed on the Falling Clock Edge
(default)
1: I2S Data is strobed on the Rising Clock Edge
53
0x35 AEQ Control
7
0x00
Reserved
6
RW
AEQ
Restart
Restart AEQ adaptation from initial (Floor) values
0: Normal operation (default)
1: Restart AEQ adaptation
Note: This bit is not self-clearing. It must be set, then
reset.
5
RW
LCBL
Override
Override LCBL Mode Set by MODE_SEL
0: LCBL controlled by MODE_SEL pin
1: LCBL controlled by register
4
RW
LCBL
Set LCBL Mode
0: LCBL Mode disabled
1: LCBL Mode enabled. AEQ Floor value is controlled
from Adaptive EQ MIN/MAX register
3:0
Reserved
57
0x39 PG Internal
7:2
Clock Enable
1
RW
0x00
PG INT
CLK
Reserved
Enable Pattern Generator Internal Clock
This bit must be set to use the Pattern Generator
Internal Clock Generation
0: Pattern Generator with external PCLK
1: Pattern Generator with internal PCLK
See TI Application Note AN-2198 for details
0
Reserved
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