DS90UB924-Q1 Datasheet, PDF (53/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

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DS90UB924-Q1
SNLS512 – APRIL 2016
8.2.2.2 Display Application
The DS90UB924-Q1, in conjunction with the DS90UB921-Q1, is intended for interfacing with a host (graphics
processor) and a display supporting 24-bit color depth (RGB888) and high-definition (720p) digital video format. It
can receive an 8-bit RGB stream with a pixel clock rate up to 96 MHz together with three control bits (VS, HS,
and DE) and four I2S audio streams.
8.2.3 Application Curves
Time (1.25 ns/DIV)
Figure 39. 96 MHz TxCLKOUT± and TxOUT0± Data Output
Time (250 ps/DIV)
Figure 40. CMLOUT of Deserializer from 96 MHz Input
Clock
9 Power Supply Recommendations
9.1 Power Up Requirements and PDB Pin
When VDDIO and VDD33 are powered separately, the VDDIO supply (1.8V or 3.3V) should ramp 100us before
the other supply, VDD33. If VDDIO is tied with VDD33, both supplies may ramp at the same time. The VDDs
(VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If the PDB pin is not
controlled by a microcontroller, a large capacitor on the pin is needed to ensure PDB arrives after all the VDDs
have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or
VDD33, it is recommended to use a 10 kΩ pull-up and a >10 uF cap to GND to delay the PDB input signal.
A minimum low pulse of 2ms is required when toggling the PDB pin to perform a hard reset.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.
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