DS90UB924-Q1 Datasheet, PDF (19/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

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DS90UB924-Q1
SNLS512 – APRIL 2016
Feature Description (continued)
7.3.9.1.1 Sample BIST Sequence
1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the
deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all zeros pattern is balanced,
scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer
and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer
goes high, and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the
PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
3. To stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test
result is held on the PASS pin. If the test ran error free, the PASS output remains HIGH. If there one or more
errors were detected, the PASS output outputs constant LOW. The PASS output state is held until a new
BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may
be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In
most cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so
forth.), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or
reducing signal condition enhancements (Rx equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 20. BIST Mode Flow Diagram
7.3.9.2 Forward Channel and Back Channel Error Checking
The deserializer, on locking to the serial stream, compares the recovered serial stream with all zeroes and
records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer.
Forward channel errors may also be read from register 0x25 ( Table 8).
The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,
as indicated by link detect status (register bit 0x1C[0] - Table 8). CRC errors are recorded in an 8-bit register in
the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer
enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST
mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or
the serializer enters BIST mode again.
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