DS90UB924-Q1 Datasheet, PDF (46/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

DS90UB924-Q1
SNLS512 – APRIL 2016
www.ti.com
Register Maps (continued)
Table 8. Serial Control Bus Registers ^{(1) (2)} (continued)
ADD
(dec)
58
59
65
68
69
73
75
86
ADD
(hex)
Register Name
Bit
0x3A I2S DIVSEL
7
6:4
3:0
0x3B Adaptive EQ
7:6
Status
5:0
0x41 Link Error Count 7:5
4
3:0
0x44 Adaptive
7:5
Equalizer
Bypass
4
3:1
0
0x45 Adaptive EQ
7:4
MIN/MAX
3:0
0x49 Map Select
7
6
5
4:0
0x4B LVDS Driver
7:2
Setting
1:0
0x56 Loop-Through
7:4
Driver
3
2:0
Register
Type
RW
RW
R
R
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
Default
(hex)
0x00
0x03
0x60
0x88
0x00
0x08
0x08
Function Description
MCLK Div
Override
Override MCLK Divider Setting
0: No override for MCLK divider (default)
1: Override divider select for MCLK
MCLK Div See Table 4
Reserved
Reserved
EQ Status
Equalizer Status
Current equalizer level set by AEQ or Override
Register
Reserved
Link Error
Count
Enable
Enable serial link data integrity error count.
1: Enable error count
0: Disable
Link Error
Count
Link error count threshold. Counter is pixel clock
based. CLK0, CLK1, and DCA are monitored for link
errors. If error count is enabled, Deserializer will lose
lock once error count reaches threshold. If disabled,
Deserializer will lose lock with one error. Video, audio,
GPIO, and I2C data bits are not checked for errors.
EQ Stage 1 EQ Stage 1 select value. Used if adaptive EQ is
Select
bypassed. Used if adaptive EQ is bypassed.
Value
Reserved
EQ Stage 2 EQ Stage 2 select value. Used if adaptive EQ is
Select
bypassed Used if adaptive EQ is bypassed.
Value
Adaptive
EQ Bypass
Bypass Adaptive EQ
Overrides Adaptive EQ search and sets the EQ to the
static value configured in this register
0: Enable adaptive EQ (default)
1: Disable adaptive EQ (to write EQ select values)
Reserved
Adaptive
EQ Floor
Adaptive Equalizer Floor Value
Sets the AEQ floor value when Long Cable Mode
(LCBL) is enabled by register or MODE_SEL
MAPSEL Returns Status of MAPSEL pin
Pin Status
MAPSEL
Override
Map Select (MAPSEL) Setting Override
0: MAPSEL set from pin
1: MAPSEL set from register
MAPSEL
Map Select (MAPSEL) Setting
0: LSBs on TxOUT3±
1: MSBs on TxOUT3±
Reserved
Reserved
LVDS V_OD 00: 400mV differential (default)
Control
01: 600mV differential
Reserved
Loop-
Through
Driver
Enable
Enable CML Loop-Through Driver
(CMLOUTP/CMLOUTN)
0: Enable
1: Disable (default)
Reserved
46
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