DS90UB924-Q1 Datasheet, PDF (43/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

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DS90UB924-Q1
SNLS512 – APRIL 2016
Register Maps (continued)
Table 8. Serial Control Bus Registers ^{(1) (2)} (continued)
ADD
(dec)
34
35
36
ADD
(hex)
Register Name
Bit
0x22 Data Path
7
Control
6
5
4
3
2
1
0
0x23 Rx Mode Status 7
6:4
3
2
1
0
0x24 BIST Control
7:4
3
2:1
0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
0x10
0x08
Function Description
Override FC Override Configuration Loaded by Forward Channel
Configuratio 0: Allow forward channel loading of this register
n
(default)
1: Disable loading of this register from the forward
channel, keeping locally written values intact
Bits [6:0] are RW if this bit is set
Reserved
DE Polarity
This bit indicates the polarity of the DE (Data Enable)
signal.
0: DE is positive (active high, idle low) (default)
1: DE is inverted (active low, idle high)
I2S
Repeater
Regen
Regenerate I2S Data From Repeater I2S Pins
0: Output packetized audio on RGB video output pins.
(default)
1: Do not output packaged audio data on RGB video
output pins.
I2S
Channel B
Enable
Override
I2S Channel B Override
0: Set I2S Channel B Disabled (default)
1: Set I2S Channel B Enable from register
18-bit Video Video Color Depth Mode
Select
0: Select 24-bit video mode (default)
1: Select 18-bit video mode
I2S
Transport
Select
Select I2S Transport Mode
0: Enable I2S Data Island Transport (default)
1: Enable I2S Data Forward Channel Frame
Transport
I2S
Channel B
Enable
I2S Channel B Enable
0: I2S Channel B disabled (default)
1: Enable I2S Channel B
Reserved
Reserved
LFMODE
Status
Low Frequency Mode (LFMODE) pin status
0: 15 ≤ TxCLKOUT ≤ 96MHz (default)
1: 5 ≤ TxCLKOUT < 15MHz
REPEAT
Status
Repeater Mode (REPEAT) pin Status
0: Non-repeater (default)
1: Repeater
BKWD
Status
Backward Compatible Mode (BKWD) Status
0: Compatible to DS90UB925/7Q (default)
1: Backward compatible to DS90UR905/7Q
I2S
Channel B
Status
I2S Channel B Mode (I2S_DB) Status
0: I2S_DB inactive (default)
1: I2S_DB active
Reserved
BIST Pin
Config
BIST Pin Configuration
0: BIST enabled from register
1: BIST enabled from pin (default)
OSC Clock
Source
Internal OSC clock select for Functional Mode or
BIST. Functional Mode when PCLK is not present and
0x03[1]=1.
00: 33 MHz Oscillator (default)
01: 33 MHz Oscillator
Note: In LFMODE=1, the internal oscillator is
12.5MHz
BIST
Enable
BIST Control
0: Disabled (default)
1: Enabled
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