DS90UB924-Q1 Datasheet, PDF (4/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

DS90UB924-Q1
SNLS512 – APRIL 2016
www.ti.com
Pin Functions (continued)
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
GPIO_REG[8 8, 10, 7, 3 I/O, LVCMOS General Purpose I/O, register access only
:5]
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
I2S_DA
I2S_DB
I2S_DC
I2S_DD
7
O, LVCMOS Digital Audio Interface I2S Data Outputs
3
Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
37
36
INTB_IN
43
I, LVCMOS Interrupt Input
with pulldown Shared with BISTC
MCLK
I2S_WC
I2S_CLK
11
O, LVCMOS Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs
10
I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8
8
SDOUT
SWC
13
O, LVCMOS Auxiliary Digital Audio Interface I2S Data Output and Word Clock
14
with pulldown Shared with GPIO1 and GPIO0
CONTROL AND CONFIGURATION
BISTC
43
I, LVCMOS BIST Clock Select
with pulldown Shared with INTB_IN
Requires a 10-KΩ pullup if set HIGH
BISTEN
9
I, LVCMOS BIST Enable
with pulldown Requires a 10-KΩ pullup if set HIGH
IDx
12
I, Analog I2C Address Select
External pullup to VDD33 is required under all conditions. DO NOT FLOAT.
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.
See Table 7
LFMODE
32
I, LVCMOS Low Frequency Mode Select
with pulldown LFMODE = 0, 15-MHz ≤ TxCLKOUT ≤ 96-MHz (Default)
LFMODE = 1, 5-MHz ≤ TxCLKOUT < 15-MHz
Requires a 10-KΩ pullup if set HIGH
MAPSEL
26
I, LVCMOS FPD-Link (OpenLDI) Output Map Select
with pulldown MAPSEL = 0, LSBs on TxOUT3± (Default)
MAPSEL = 1, MSBs on TxOUT3±
Requires a 10-KΩ pullup if set HIGH
MODE_SEL
48
I, Analog
Device Configuration Select
Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4 channel (I2S_B),
and Long Cable (LCBL) modes
Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage
divider. DO NOT FLOAT
See Table 6
OEN
30
I, LVCMOS Output Enable
with pulldown Requires a 10-KΩ pullup if set HIGH
See Table 5
OSS_SEL
35
I, LVCMOS Output Sleep State Select
with pulldown Requires a 10 KΩ pullup if set HIGH
See Table 5
PDB
SCL
1
I, LVCMOS Power-down Mode Input Pin
Must be driven or pulled up to VDD33. Refer to Power Up Requirements and PDB PinPower
Up Requirements and PDB Pin in Application and Implementation.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down
When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,
the PLL is shutdown, and I_DD is minimized. Control Registers are RESET.
5
I/O, Open I²C Clock Input/Output Interface
Drain
Must have an external pullup to V_DD33. DO NOT FLOAT
Recommended pullup: 4.7 KΩ
SDA
4
I/O, Open I2C Data Input/Output Interface
Drain
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
4
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