DS90UB924-Q1 Datasheet, PDF (5/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

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DS90UB924-Q1
SNLS512 – APRIL 2016
Pin Functions (continued)
PIN
NAME
NO.
STATUS
LOCK
27
I/O, TYPE
O, LVCMOS
PASS
28
O, LVCMOS
FPD-LINK III SERIAL INTERFACE
CMF
42
Analog
CMLOUTN
45
O, LVDS
CMLOUTP
44
O, LVDS
RIN-
41
I/O, LVDS
RIN+
40
POWER AND GROUND ⁽¹⁾
GND
DAP
I/O, LVDS
Ground
VDD33_A
38
Power
VDD33_B
31
VDDIO
6
Power
REGULATOR CAPACITOR
CAPI2S
2
CAPLV25
25
CAPLV12
29
CAPR12
46
CAPP12
47
CAPL12
33
CAP
CAP
OTHER
RES[1:0]
39, 34
GND
DESCRIPTION
LOCK Status Output
0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states
controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.
1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL
Route to test point or pad (recommended). Float if unused.
PASS Status Output
0: One or more errors were detected in the received BIST payload (BIST Mode)
1: Error-free transmission (BIST Mode)
Route to test point or pad (Recommended). Float if unused.
Common Mode Filter
Requires a 0.1-µF capacitor to GND
Inverting Loop-through Driver Output
Monitor point for equalized forward channel differential signal
True Loop-through Driver Output
Monitor point for equalized forward channel differential signal
FPD-Link III Inverting Input
The output must be AC-coupled with a 0.1-µF capacitor
FPD-Link III True Input
The output must be AC-coupled with a 0.1-µF capacitor
Large metal contact at the bottom center of the device package
Connect to the ground plane (GND) with at least 9 vias
3.3-V power to on-chip regulator
Each pin requires a 4.7-µF capacitor to GND
1.8-V / 3.3-V LVCMOS I/O Power
Requires a 4.7-µF capacitor to GND
Decoupling capacitor connection for on-chip regulator
Each requires a 4.7-µF decoupling capacitor to GND
Decoupling capacitor connection for on-chip regulator
Requires two 4.7-µF decoupling capacitors to GND
Reserved
Connect to GND
(1) The V_DD (V_DD33 and V_DDIO) supply ramp must be faster than 1.5 ms with a monotonic rise.
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