DS90UB924-Q1 Datasheet, PDF (26/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

DS90UB924-Q1
SNLS512 – APRIL 2016
Table 4. Audio Interface Frequencies (continued)
SAMPLE RATE
(kHz)
I2S DATA WORD SIZE (BITS) I2S_CLK (MHz)
32
1.536
44.1
2.117
48
24
2.304
96
4.608
192
9.216
32
2.048
44.1
2.8224
48
32
3.072
96
6.144
192
12.288
MCLK OUTPUT (MHz)
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
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REGISTER 0x3A[6:4]'b
000
001
010
001
010
011
001
010
011
010
011
100
011
100
101
001
010
011
001
010
011
001
010
011
010
011
100
011
100
110
7.3.16 AV Mute Prevention
The DS90UB924-Q1 may inadvertently enter the AV MUTE state if the serializer sends video data during
blanking period (DE = L) with a specific data pattern (24’h666666). Once the device enters the AV MUTE
state, the device mutes both audio and video outputs resulting in a black display screen. Setting the gate DE
Register 0x04[4] on the serializer will prevent video signals from being sent during the blanking interval. This
will ensure AV MUTE mode is not entered during normal operation
If unexpected AV MUTE state is seen, it is recommended to verify checking the data path control setting of
the paired Serializer. This setting is not accessible from DS90UB924-Q1.
7.3.17 OEN Toggling Limitation
OEN must be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN
function is asynchronous signal to internal digital blocks, repeatedly OEN toggling may result in horizontal pixel
shift at the LVDS output. To avoid this, recommend to reset by programming Register 0x01[0] for digital blocks
after OEN turns to ON state.
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