English
Language : 

DS90UB924-Q1 Datasheet, PDF (52/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel
DS90UB924-Q1
SNLS512 – APRIL 2016
Typical Application (continued)
HOST
Graphics
Processor
VDDIO VDD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
I2S AUDIO 3
(STEREO)
DOUT+
DOUT-
DS90UB921-Q1
Serializer
SCL
SDA
IDx
DAP
FPD-Link III
1 Pair/AC Coupled
100Q STP Cable
OEN
OSS_SEL
MODE_SEL
PDB
INTB
MAPSEL
LFMODE
BISTEN
MODE_SEL
FPD-Link
(Open LDI)
VDD33
VDDIO
(3.3V) (1.8V or 3.3V)
RIN+
RIN-
DS90UB924-Q1
Deserializer
TxOUT3+/-
TxOUT2+/-
TxOUT1+/-
TxOUT0+/-
TxCLKOUT+/-
INTB_IN
LOCK
6
PASS
I2S
MCLK
SCL
SDA
IDx
www.ti.com
LVDS Display
720p or
Graphic
Proccesor
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Typical Display System Diagram
8.2.1 Design Requirements
For the typical design application, use the following as input parameters:
Table 9. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for RIN±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
330nF for RIN+, 250nF for RIN-
(Single-ended)
100 nF for RIN+/- (Differential)
96 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Transmission Media
The DS90UB927Q-Q1/DS90UB921-Q1/DS90UB925Q-Q1 and DS90UB924-Q1 chipset is intended to be used in
a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide
internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the
serializer and deserializer must have a differential impedance of 100 Ω. The maximum length of cable that can
be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power
plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency,
and so forth.) and the application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width and eye opening height. use a differential probe to measure across the
termination resistor at the CMLOUTP/CMLOUTN pins.
52
Submit Documentation Feedback
Product Folder Links: DS90UB924-Q1
Copyright © 2016, Texas Instruments Incorporated