DS90UB924-Q1 Datasheet, PDF (25/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

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DS90UB924-Q1
SNLS512 – APRIL 2016
7.3.15.2 I2S Repeater
I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via data
island transport on the FPD-Link (OpenLDI) interface during the video blanking periods. If frame transport is
desired, connect the I2S pins from the deserializer to all serializers. Activating surround sound at the top-level
serializer automatically configures downstream serializers and deserializers for surround-sound transport utilizing
Data Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be
explicitly set in each serializer and deserializer control register throughout the repeater tree (Table 8).
A DS90UB924-Q1 deserializer configured in repeater mode may also regenerate I2S audio from its I2S input
pins in lieu of Data Island frames. See Figure 31 and the I2C control registers (Table 8) for additional details.
7.3.15.3 I2S Jitter Cleaning
The DS90UB924-Q1 features a standalone PLL to clean the I2S data jitter, supporting high-end car audio
systems. If I2S_CLK frequency is less than 1 MHz, this feature must be disabled through register 0x2B[7]. See
Table 8.
7.3.15.4 MCLK
The deserializer has an I2S Master Clock Output (MCLK). It supports ×1, ×2, or ×4 of I2S CLK Frequency. When
the I2S PLL is disabled, the MCLK output is off. Table 4 covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are ×2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 8. To select
desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.
SAMPLE RATE
(kHz)
32
44.1
48
96
192
Table 4. Audio Interface Frequencies
I2S DATA WORD SIZE (BITS) I2S_CLK (MHz)
1.024
1.4112
16
1.536
3.072
6.144
MCLK OUTPUT (MHz)
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
REGISTER 0x3A[6:4]'b
000
001
010
000
001
010
000
001
010
001
010
011
010
011
100
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