DS90UB924-Q1 Datasheet, PDF (55/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

www.ti.com
DS90UB924-Q1
SNLS512 – APRIL 2016
9.2 Analog Power Signal Routing
All power inputs must be tied to the main VDD source (for example, battery), unless the user wishes to power it
from another source. (that is, external LDO output).
The analog VDD inputs power the internal bias and error amplifiers, so they must be tied to the main VDD. The
analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended
Operating Conditions table earlier in the datasheet.
The other VINs (VINLDO1, VINLDO2) can have inputs lower than 2.8 V, as long as the input it higher than the
programmed output (0.3 V).
The analog and digital grounds must be tied together outside of the chip to reduce noise coupling.
10 Layout
10.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide
low-noise power to the device. Good layout practice also separates high frequency or high-level inputs and
outputs to minimize unwanted stray noise, feedback, and interference. Power system performance may be
greatly improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes
the plane capacitance for the PCB power system and has low inductance, which has proven effectiveness
especially at high frequencies, and makes the value and placement of external bypass capacitors less critical.
External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors may use
values in the range of 0.01 μF to 10 μF. Tantalum capacitors may be in the 2.2 μF to 10 μF range. The voltage
rating of the capacitors must be at least 5X the power supply voltage being used.
TI recommends MLCC surface mount capacitors due to their smaller parasitic properties. When using multiple
capacitors per supply pin, locate the smaller value closer to the pin. TI recommends a large bulk capacitor
typically in the 50 μF to 100 μF range at the point of power entry, which smooths low frequency switching noise
connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the
plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor
increases the inductance of the path. TI recommends a small body size X7R chip capacitor, such as 0603 or
0805, for external bypass. Because a small body sized capacitor has less inductance. The user must pay
attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 MHz to 30
MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the
supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from
power and ground pins to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs. This device requires only one common ground plane to connect all device related ground pins.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω
are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.
At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device
ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB
ground plane. More information on the WQFN package, including PCB design and manufacturing requirements,
is provided in AN-1187 Leadless Leadframe Package (LLP) (AN-2198).
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB924-Q1
Submit Documentation Feedback
55