DS90UB924-Q1 Datasheet, PDF (22/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

DS90UB924-Q1
SNLS512 – APRIL 2016
Feature Description (continued)
www.ti.com
NOTE
The device detects any of the above conditions, but does not report specifically which one
has occurred.
7.3.12 Oscillator Output
The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost.
This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable)
Table 8.
7.3.13 Interrupt Pin (INTB / INTB_IN)
1. Read HDCP_ISR Register 0xC7. (Table 8)
2. On the serializer, set register (ICR) 0xC6[5] = 1 and 0xC6[0] = 1 to configure the interrupt.
3. On the serializer, read from ISR register 0xC7 to arm the interrupt for the first time.
4. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
5. The external controller detects INTB = LOW and reads the ISR register to determine the interrupt source.
Reading this register also clears and resets the interrupt.
The INTB_IN signal is sampled and required approximately 8.6 μs of the minimum setup and hold time.
8.6 μs = 30 bit per back channel frame / (5 Mbps rate × ±30% Variation) = 30 / (5E6 × 0.7)
Note that -30% is the worst case.
7.3.14 General-Purpose I/O
7.3.14.1 GPIO[3:0]
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO modes may be configured from the registers (Table 8). GPIO[1:0] are dedicated
pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UB924-Q1 is paired with
a DS90UB921-Q1 or DS90UB925Q-Q1 serializer, the devices must be configured into 18-bit mode to allow
usage of GPIO pins on the serializer. To enable 18-bit mode, set serializer register 0x12[2] = 1. 18-bit mode is
auto-loaded into the deserializer from the serializer. See Table 1 for GPIO enable and configuration.
Table 1. DS90UB921-Q1/DS90UB925Q-Q1 GPIO Enable and Configuration
DESCRIPTION
GPIO3
GPIO2
GPIO1/GPIO1
(SER/DES)
GPO_REG5/GPIO1
(SER/DES)
GPIO0/GPIO0
(SER/DES)
GPO_REG4/GPIO0
(SER/DES)
DEVICE
DS90UB921-Q1/
DS90UB925Q-Q1
DS90UB924-Q1
DS90UB921-Q1/
DS90UB925Q-Q1
DS90UB924-Q1
DS90UB921-Q1/
DS90UB925Q-Q1
DS90UB924-Q1
DS90UB921-Q1/
DS90UB925Q-Q1
DS90UB924-Q1
DS90UB921-Q1/
DS90UB925Q-Q1
DS90UB924-Q1
DS90UB921-Q1/
DS90UB925Q-Q1
DS90UB924-Q1
FORWARD CHANNEL
0x0F = 0x03
0x1F = 0x05
0x0E = 0x30
0x1E = 0x50
N/A
N/A
0x10 = 0x03
0x1E = 0x05
N/A
N/A
0x0F = 0x30
0x1D = 0x05
BACK CHANNEL
0x0F = 0x05
0x1F = 0x03
0x0E = 0x50
0x1E = 0x30
0x0E = 0x05
0x1E = 0x03
N/A
N/A
0x0D = 0x05
0x1D = 0x03
N/A
N/A
22
Submit Documentation Feedback
Product Folder Links: DS90UB924-Q1
Copyright © 2016, Texas Instruments Incorporated