DS90UB924-Q1 Datasheet, PDF (50/62 Pages) Texas Instruments – 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With Bidirectional Control Channel

DS90UB924-Q1
SNLS512 – APRIL 2016
8 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90UB924-Q1 deserializer, in conjunction with a DS90UB921-Q1, DS90UB925Q-Q1 or DS90UB927Q-Q1
serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. It
converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link
III), to four LVDS data/control streams, one LVDS clock pair (FPD-Link (OpenLDI)), and I2S audio data. The
serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission, and low-speed full
duplex back channel communication over a single differential link. Consolidation of audio, video data, and control
over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and
simplifying system design.
8.2 Typical Application
Figure 37 shows a typical application of the DS90UB924-Q1 deserializer for an 96 MHz 24-bit color display
application. Inputs utilize 0.1-µF coupling capacitors to the line, and the deserializer provides internal termination.
The voltage rating of the coupling capacitors must be ≥50 V and must use a small body capacitor size, such as
0402 or 0602, to help ensure good signal integrity. The FPD-Link (OpenLDI) LVDS differential outputs require
100-Ω termination resistors at the receiving device or display.
Bypass capacitors must be placed near the power supply pins. At a minimum, three 4.7-μF capacitors, one
placed at each power supply pin, are required for local device bypassing. If additional bypass capacitors are
used, place the smaller value components closer to the pin. Ferrite beads are required on the two supplies
(V_DD33 and V_DDIO) for effective noise suppression. Connect pins VDD33_A and VDD33_B directly to ensure ESD
performance. The interface to the display is FPD-Link (OpenLDI) LVDS. The VDDIO pin may be connected to 3.3
V or 1.8 V. Place a delay capacitor (>10 µF) and pullup resistor (10 kΩ) on the PDB signal to delay the enabling
of the device until power is stable.
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