LM3S300-IQN25-C2 Datasheet, PDF (9/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S300 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S300 Microcontroller High-Level Block Diagram ................................. 33
Figure 2-1. CPU Block Diagram ............................................................................................. 42
Figure 2-2. TPIU Block Diagram ............................................................................................ 43
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 45
Figure 2-4. Bit-Band Mapping ................................................................................................ 65
Figure 2-5. Data Storage ....................................................................................................... 66
Figure 2-6. Vector Table ........................................................................................................ 71
Figure 2-7. Exception Stack Frame ........................................................................................ 73
Figure 3-1. SRD Use Example ............................................................................................... 88
Figure 4-1. JTAG Module Block Diagram .............................................................................. 141
Figure 4-2. Test Access Port State Machine ......................................................................... 144
Figure 4-3. IDCODE Register Format ................................................................................... 148
Figure 4-4. BYPASS Register Format ................................................................................... 149
Figure 4-5. Boundary Scan Register Format ......................................................................... 149
Figure 5-1. Basic RST Configuration .................................................................................... 152
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 152
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 153
Figure 5-4. Main Clock Tree ................................................................................................ 156
Figure 6-1. Flash Block Diagram .......................................................................................... 205
Figure 7-1. GPIO Port Block Diagram ................................................................................... 225
Figure 7-2. GPIODATA Write Example ................................................................................. 226
Figure 7-3. GPIODATA Read Example ................................................................................. 226
Figure 8-1. GPTM Module Block Diagram ............................................................................ 263
Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 267
Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 268
Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 269
Figure 9-1. WDT Module Block Diagram .............................................................................. 299
Figure 10-1. UART Module Block Diagram ............................................................................. 323
Figure 10-2. UART Character Frame ..................................................................................... 324
Figure 11-1. SSI Module Block Diagram ................................................................................. 362
Figure 11-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 365
Figure 11-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 366
Figure 11-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 366
Figure 11-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 367
Figure 11-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 368
Figure 11-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 368
Figure 11-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 369
Figure 11-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 370
Figure 11-10. MICROWIRE Frame Format (Single Frame) ........................................................ 370
Figure 11-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 371
Figure 11-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 372
Figure 12-1. I²C Block Diagram ............................................................................................. 401
Figure 12-2. I²C Bus Configuration ........................................................................................ 402
Figure 12-3. START and STOP Conditions ............................................................................. 402
Figure 12-4. Complete Data Transfer with a 7-Bit Address ....................................................... 403
Figure 12-5. R/S Bit in First Byte ............................................................................................ 403
June 18, 2012
9
Texas Instruments-Production Data