LM3S300-IQN25-C2 Datasheet, PDF (10/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Figure 12-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 403
Figure 12-7. Master Single SEND .......................................................................................... 406
Figure 12-8. Master Single RECEIVE ..................................................................................... 407
Figure 12-9. Master Burst SEND ........................................................................................... 408
Figure 12-10. Master Burst RECEIVE ...................................................................................... 409
Figure 12-11. Master Burst RECEIVE after Burst SEND ............................................................ 410
Figure 12-12. Master Burst SEND after Burst RECEIVE ............................................................ 411
Figure 12-13. Slave Command Sequence ................................................................................ 412
Figure 13-1. Analog Comparator Module Block Diagram ......................................................... 437
Figure 13-2. Structure of Comparator Unit .............................................................................. 438
Figure 13-3. Comparator Internal Reference Structure ............................................................ 440
Figure 14-1. 48-Pin QFP Package Pin Diagram ...................................................................... 449
Figure 17-1. Load Conditions ................................................................................................ 462
Figure 17-2. JTAG Test Clock Input Timing ............................................................................. 463
Figure 17-3. JTAG Test Access Port (TAP) Timing .................................................................. 463
Figure 17-4. JTAG TRST Timing ............................................................................................ 464
Figure 17-5. External Reset Timing (RST) .............................................................................. 464
Figure 17-6. Power-On Reset Timing ..................................................................................... 465
Figure 17-7. Brown-Out Reset Timing .................................................................................... 465
Figure 17-8. Software Reset Timing ....................................................................................... 465
Figure 17-9. Watchdog Reset Timing ..................................................................................... 466
Figure 17-10. LDO Reset Timing ............................................................................................. 466
Figure 17-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 467
Figure 17-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 468
Figure 17-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 468
Figure 17-14. I²C Timing ......................................................................................................... 469
Figure D-1. Stellaris LM3S300 48-Pin LQFP Package ........................................................... 493
Figure D-2. 48-Pin LQFP Tray Dimensions ........................................................................... 495
Figure D-3. 48-Pin LQFP Tape and Reel Dimensions ............................................................. 497
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June 18, 2012
Texas Instruments-Production Data