LM3S300-IQN25-C2 Datasheet, PDF (264/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

General-Purpose Timers
NRND: Not recommended for new designs.
Table 8-2. General-Purpose Timers Signals (48QFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
CCP3
2
I/O
TTL
Capture/Compare/PWM 3.
CCP4
4
I/O
TTL
Capture/Compare/PWM 4.
CCP5
1
I/O
TTL
Capture/Compare/PWM 5.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
8.3 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 274),
the GPTM TimerA Mode (GPTMTAMR) register (see page 275), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 277). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
8.3.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 288) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 289). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 292) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 293).
8.3.2
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 288
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 289
■ GPTM TimerA (GPTMTAR) register [15:0], see page 296
■ GPTM TimerB (GPTMTBR) register [15:0], see page 297
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
264
June 18, 2012
Texas Instruments-Production Data