LM3S300-IQN25-C2 Datasheet, PDF (205/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S300 Microcontroller
6 Internal Memory
The LM3S300 microcontroller comes with 4 KB of bit-banded SRAM and 16 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
6.1 Block Diagram
Figure 6-1 on page 205 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.
Figure 6-1. Flash Block Diagram
Cortex-M3
Icode Bus
Dcode Bus
Flash Control
FMA
FMD
FMC
FCRIS
FCIM
FCMISC
Flash Array
Bridge
Flash Protection
FMPRE
FMPPE
Flash Timing
USECRL
SRAM Array
6.2
6.2.1
Functional Description
This section describes the functionality of the SRAM and Flash memories.
SRAM Memory
The internal SRAM of the Stellaris^® devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
June 18, 2012
205
Texas Instruments-Production Data