LM3S300-IQN25-C2 Datasheet, PDF (462/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

Electrical Characteristics
NRND: Not recommended for new designs.
Figure 17-1. Load Conditions
pin
C_L = 50 pF
GND
17.2.2
17.2.3
Clocks
Table 17-7. Phase Locked Loop (PLL) Characteristics
Parameter Parameter Name
Min
Nom
Max
Unit
f_{ref_crystal}
f_{ref_ext}
f_pll
Crystal reference^a
External clock reference^a
PLL frequency^b
3.579545
-
3.579545
-
-
200
8.192
8.192
-
MHz
MHz
MHz
T_READY
PLL lock time
-
-
0.5
ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 17-8. Clock Characteristics
Parameter
f_IOSC
f_MOSC
t_{MOSC_per}
f_{ref_crystal_bypass}
f_{ref_ext_bypass}
f_{system_clock}
Parameter Name
Internal oscillator frequency
Main oscillator frequency
Main oscillator period
Crystal reference using the main oscillator
(PLL in BYPASS mode)
External clock reference (PLL in BYPASS
mode)
System clock
JTAG and Boundary Scan
Min
Nom
7
12
1
-
125
-
1
-
0
-
0
-
Max
22
8
1000
8
25
25
Unit
MHz
MHz
ns
MHz
MHz
MHz
Table 17-9. JTAG Characteristics
Parameter
No.
J1
J2
J3
J4
J5
J6
J7
J8
J9
Parameter Parameter Name
f_TCK
t_TCK
t_{TCK_LOW}
t_{TCK_HIGH}
t_{TCK_R}
t_{TCK_F}
t_{TMS_SU}
t_{TMS_HLD}
t_{TDI_SU}
TCK operational clock frequency
TCK operational clock period
TCK clock Low time
TCK clock High time
TCK rise time
TCK fall time
TMS setup time to TCK rise
TMS hold time from TCK rise
TDI setup time to TCK rise
Min
Nom
0
-
100
-
-
t_TCK/2
-
t_TCK/2
0
-
0
-
20
-
20
-
25
-
Max
10
-
-
-
10
10
-
-
-
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
462
June 18, 2012
Texas Instruments-Production Data