LM3S300-IQN25-C2 Datasheet, PDF (17/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S300 Microcontroller
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 348
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 350
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 351
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 352
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 353
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 354
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 355
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 356
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 357
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 358
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 359
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 360
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 361
Synchronous Serial Interface (SSI) ............................................................................................ 362
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 375
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 377
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 379
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 380
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 382
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 383
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 385
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 386
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 387
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 388
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 389
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 390
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 391
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 392
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 393
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 394
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 395
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 396
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 397
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 398
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 399
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 400
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 415
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 416
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 420
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 421
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 422
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 423
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 424
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 425
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 426
Register 10: I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 428
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 429
June 18, 2012
17
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