LM3S300-IQN25-C2 Datasheet, PDF (161/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S300 Microcontroller
Table 5-5. System Control Register Map (continued)
Offset Name
Type
Reset
Description
0x124
0x128
0x144
0x150
0x160
DCGC1
DCGC2
DSLPCLKCFG
CLKVCLR
LDOARST
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 2
R/W
0x0780.0000 Deep Sleep Clock Configuration
R/W
0x0000.0000 Clock Verification Clear
R/W
0x0000.0000 Allow Unregulated LDO to Reset the Part
5.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
194
199
174
175
176
June 18, 2012
161
Texas Instruments-Production Data