LM3S300-IQN25-C2 Datasheet, PDF (16/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 279
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 282
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 284
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 285
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 286
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 288
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 289
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 290
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 291
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 292
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 293
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 294
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 295
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 296
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 297
Watchdog Timer ........................................................................................................................... 298
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 302
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 303
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 304
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 305
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 306
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 307
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 308
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 309
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 310
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 311
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 312
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 313
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 314
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 315
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 316
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 317
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 318
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 319
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 320
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 321
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 322
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 330
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 332
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 334
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 336
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 337
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 338
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 340
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 342
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 344
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 346
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 347
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June 18, 2012
Texas Instruments-Production Data