LM3S300-IQN25-C2 Datasheet, PDF (22/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

Revision History
NRND: Not recommended for new designs.
Table 1. Revision History (continued)
Date
November 2008
Revision Description
4283 ■ Revised High-Level Block Diagram.
■ Corrected descriptions for UART1 signals.
■ Additional minor data sheet clarifications and corrections were made.
October 2008
4149
■ Added note on clearing interrupts to the Interrupts chapter:
Note:
It may take several processor cycles after a write to clear an interrupt source in order for
NVIC to see the interrupt source de-assert. This means if the interrupt clear is done as
the last action in an interrupt handler, it is possible for the interrupt handler to complete
while NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This can be avoided by either clearing the interrupt source at the
beginning of the interrupt handler or by performing a read or write after the write to clear
the interrupt source (and flush the write buffer)
■ Bit 13 and bit 5 of the GPTM Control (GPTMCTL) register should have been marked as reserved
for Stellaris^® devices without an ADC module.
■ Additional minor data sheet clarifications and corrections were made.
June 2008
2972 Started tracking revision history.
22
June 18, 2012
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