LM3S300-IQN25-C2 Datasheet, PDF (30/498 Pages) Texas Instruments – Stellaris LM3S300 Microcontroller

Architectural Overview
NRND: Not recommended for new designs.
– Line-break generation and detection
– Fully programmable serial interface characteristics
• 5, 6, 7, or 8 data bits
• Even, odd, stick, or no-parity bit generation/detection
• 1 or 2 stop bit generation
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ I²C
– Devices on the I²C bus can be designated as either a master or a slave
• Supports both sending and receiving data as either a master or a slave
• Supports simultaneous master and slave operation
– Four I²C modes
• Master transmit
• Master receive
• Slave transmit
• Slave receive
– Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
– Master and slave interrupt generation
• Master generates interrupts when a transmit or receive operation completes (or aborts
due to an error)
• Slave generates interrupts when data has been sent or requested by a master
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ Analog Comparators
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June 18, 2012
Texas Instruments-Production Data