THS8200 Datasheet, PDF (87/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

7.3.3 Analog (DAC) Outputs
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
DAC resolution
10
10
(11 bit internal) (11 bit internal)
bits
INL
Integral nonlinearity
Best-fit
VDD_IO =
3.3 V, CLK =
500 kHz
Video (0.7 + 0.35 V
bias)
Generic (1.25 + 0 V
bias)
+0.5/–1.2 +2/–2
LSB
+1/–2.1 +5/–5
DNL
Differential nonlinearity
VDD_IO =
3.3 V, CLK =
500 kHz
Video (0.7 + 0.35 V
bias)
Generic (1.25 + 0 V
bias)
+0.2/–0.3 +1/–1
LSB
+0.3/–0.5 +1/–1
PSRR
Power supply ripple rejection
ratio of DAC output (full scale)
f = dc to 100 kHz, See Note 1
40
42
dB
XTALK Crosstalk between channels
CLK = 205
MHz, –1 dB
sine wave
applied to
active
channel,
offset bias
applied to all
channels
when turned
on, 37.5 Ω
load on all
channels
1 MHz sine wave, offset
bias off
1 MHz sine wave, offset
bias on
10 MHz sine wave,
offset bias off
10 MHz sine wave,
offset bias on
30 MHz sine wave,
offset bias off
30 MHz sine wave,
offset bias on
49
42
49
dB
42
48
40.5
KIMBAL Imbalance between DACs
VOC
DAC output compliance
voltage (video only)
CLK = 80 MHz See Note 3
RL = 37.5 Ω,
See Note 4
Video mode (bias offset
can be added)
Generic mode (bias
offset cannot be added)
±2%
0.7 0.72
V
1.25 1.3
DAC output capacitance (pin
Co
capacitance)
5
pF
tri
DAC output current rise time 10 to 90% of full-scale, CLK = 80 MHz
tfi
DAC output current fall time
10 to 90% of full-scale, CLK = 80 MHz
td
Analog output delay
Measured from falling edge of CLKIN to
50% of full-scale transition, See Note 5
3.5 4.2 ns
3.5 4.2 ns
6.5
ns
Measured from 50% of full scale
tsa
Analog output settling time
transition on output to output settling,
within 2%, See Note 6
6.6
ns
SFDR Spurious-free dynamic range 1 MHz, –1 dB FS digital sine input
–55
dB
SFDR Spurious-free dynamic range 10 MHz, –1 dB FS digital sine input
–43
dB
BW
Bandwidth (3 dB)
90
MHz
Eglitch
NOTES:
Glitch energy
Full-scale code transition at 205 MSPS
25
pVs
1. PSRR is defined as 20*log (ripple voltage at DAC output/ripple voltage at AVDD input). Limits from characterization only.
2. Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limit from characterization only.
3. The imbalance between DACs applies to all possible pairs of the three DACs.
4. Nominal values at RFS = RFS(nom), see figure in Section 7.7. Limit from characterization only. Excludes bias offset.
5. This value excludes the digital process delay, tD(D). Limit from characterization only. Data is clocked in on the rising edge of CLKIN.
Analog outputs become available on the falling edge of CLKIN.
6. Limit from characterization only.
7–4