THS8200 Datasheet, PDF (12/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

Table 2–1. Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE^†
DESCRIPTION
RCr[9:0]
33–42
I
10-bit video data input port. All 10-bits or the 8 MSB of this port can be connected to the video data source. In
30-bit mode, the R data of RGB or the Cr data of YCbCr should be connected to this port. In the 10- /20-bit
input mode, this port is unused. For some input formats this port is unused.
RESETB
60
SCL
64
SDA
63
I
Software reset pin (active low). The minimum reset duration is 200 ns.
B Serial clock line of I2C bus interface. Open-collector. Maximum specified clock speed is 400 kHz (fast I2C).
B Serial data line of I2C bus interface. Open-collector
VDD_DLL
4
PWR Power supply of clock doubler, nominal 1.8 V
VDD_IO 19, 46, 70 PWR I/O ring power, 1.8 V or 3.3 V nominal
VS_IN
44
I/O Vertical source synchronization. In slave timing mode, this is an input from the video data source. In master
timing mode, this is an output to the video data source with programmable timing and polarity, serving as a
vertical data qualification signal to the video source.
VS_OUT
62
O Vertical sync output (to display). Irrespective of slave/master timing mode configuration, this is always an
output with timing generated by the DTG.
† _{I = input, O = output, B = bidirectional, PWR = power or ground, P = passive}
2–3