THS8200 Datasheet, PDF (86/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

7.3.2 Digital Inputs—DC Characteristics
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
IIH
IIL
IIL(CLK)
IIH(CLK)
CI
ts
tH
High-level input current
Low-level input current
Low-level input current, CLK
High-level input current, CLK
Input capacitance
Data and control inputs setup time
Data and control inputs hold time
td(D)
Digital process delay(1)
VDD_IO = 3.3 V,
Digital inputs and CLK at 0 V for IIL;
Digital inputs and CLK at 3.6 V for IIH
TA = 25°C
10-bit/20-bit 4:2:2 with CSM, CSC, and 2
interpolation active
30-bit 4:4:4
VESA clock mode (DLL, CSM, CSC, FIRs
bypassed)
5
1.5
0.5
73(2)
33(2)
9
1
–1
µA
1
–1
pF
ns
ns
pixels
NOTES:
1. Defined as the delay on Y pixel data, starting from the rising edge of CLKIN, until the clock period when corresponding analog output
becomes available. Because analog output starts to become available on falling edge of CLKIN, an additional 1/2 cycle is to be added
to this delay.
2. CSC contribution, 8 pixels; CSM contribution, 1 pixel; 2 interpolation filter contribution, 18 pixels
7–3