THS8200 Datasheet, PDF (67/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

csc_bypass:
Bypass for CSC block
{csc_offs3 0x19(1)} [1]
0 : Color space conversion (CSC) not bypassed
1 : CSC bypassed
csc_uof_cntl:
Under-/overflow control for CSC block
{csc_offs3 0x19(1)} [0]
Controls over-/underflow protection logic on color space converter
0 : Under-/overflow protection off
1 : Under-/overflow protection on
5.1.3 Test Control (Sub-Addresses 0x1A–0x1B)
tst_digbypass:
Bypass to DAC inputs
{tst_cntl1 0x1A(7)} [0]
0 : Normal operation; nonbypass
1 : Digital logic bypassed to directly control DACs from input bus
tst_offset:
Bypass for DAC offsets
{tst_cntl1 0x1A(6)} [0]
0 : Normal operation; logic not bypassed
1 : Programmed offsets are always added to DAC codes regardless of mode or dtg_state.
tst_ydelay(1:0):
Y delay path control
{tst_cntl2 0x1B(7:6)} [00]
Adjusts the delay of the Y channel during YCbCr modes.
tst_fastramp:
DAC test control, fast ramp
{tst_cntl2 0x1B(1)} [0]
0 : Normal operation
1 : DAC outputs a ramp at 2× clock rate.
tst_slowramp:
DAC test control, slow ramp
{tst_cntl2 0x1B(0)} [0]
0 : Normal operation
1 : DAC outputs a ramp at 2× clock rate divided by 64,000. This mode has a higher priority than the one set by
tst_fastramp.
5.1.4 Data Path Control (Sub-Address 0x1C)
data_clk656_on:
{data_cntl 0x1C(7)} [0]
0 : D1CLKO output off
1 : D1CLKO output on
ITU-R.BT656 output clock control
5–10