THS8200 Datasheet, PDF (76/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

dtg2_hs_in_dly(12:0): DTG horizontal delay
{dtg2_hs_in_dly_msb 0x79(4:0) and dtg2_hs_in_dly_lsb 0x7A(7:0)} [0 0000 0011 1101]
Sets the number of pixels that the DTG startup is horizontally delayed with respect to HS input for dedicated timing
modes or EAV input for embedded timing modes.
Note: It is possible to delay startup past the end of a line when this delay is programmed higher than the total number
of pixels per line.
dtg2_vs_in_dly(10:0): DTG vertical delay
{dtg2_vs_in_dly_msb 0x7B(2:0) and dtg2_vs_in_dly_lsb 0x7C(7:0)} [000 0000 0011]
Sets the number of lines that the DTG startup is vertically delayed with respect to VS input for dedicated timing
modes or the line counter value for embedded timing.
Note: It is possible to delay startup past the end of a frame when this delay is programmed higher than the total
number of lines per frame.
dtg2_pixel_cnt(15:0): Pixel count readback
{dtg2_pixel_cnt_msb 0x7D(7:0) and dtg2_pixel_cnt_lsb 0x7E(7:0)}
Reports the number of clock 1 rising edges between consecutive Hsync input pulses
dtg2_ip_fmt:
Interlaced/progressive-scan indicator
{dtg2_line_cnt_msb 0x7F(7)
Indicates whether current video frame is progressive (0) or interlaced (1)
dtg2_line_cnt(10:0): Line count readback
{dtg2_lined_cnt_msb 0x7F(2:0) and dtg2_line_cnt_lsb 0x80(7:0)}
Reports the number of Hsync input pulses between consecutive dtg_start signals (i.e., over one frame period)
dtg2_fid_de_cntl:
FID (field-ID)/DE (data enable)input selection for FID terminal
{dtg2_cntl 0x82(7)} [0]
Controls interpretation of signal on FID terminal
0 : Signal interpeted as FieldID
1 : If the DTG is programmed to the VESA mode, the FID pin becomes a data-enable input pin. Data enable is
assumed high during the active video window, and low outside this area. This is compatible with the DE signal from
TI DVI receivers. Data is passed through the THS8200 only when data enable is high. Otherwise, the input data is
overridden by the THS8200 internally programmed blanking value. If the DTG is programmed in the SDTV or HDTV
video mode with dedicated timing signals, a 1 in this register location causes the THS8200 to generate an internal
FieldID value from the relative alignment of Hsync and Vsync inputs, rather than using the signal on the FID input pin
(which is ignored). This is for EIA-861 compliant operation for video-over-DVI 1.0 (with HDCP) where there is no
dedicated FID signal available but the even/odd field ID is determined from Hsync/Vsync alignment.
dtg2_rgb_mode_on: RGB/YPbPr mode selection
{dtg2_cntl 0x82(6)} [1]
This selection affects the relative blank vs video level position: on R,G,B, and Y channels an offset is added to the
DAC outputs
0 : YPbPr mode (blanking at bottom range for Y – mid-range for Pb, Pr channels)
1 : RGB mode (blanking at bottom ranges for all channels)
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