THS8200 Datasheet, PDF (15/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

EIA.770-1 (10:4 video/sync ratio) and EIA.770-2 (7:3 video/sync ratio) compliant analog component video outputs,
and to support nonstandard video timing formats.
In addition or as an alternative to the composite sync inserted on green/luma channel or all analog outputs, output
video timing can be carried via dedicated Hsync/Vsync output signals as well. The position, duration and polarity of
Hsync and Vsync outputs are fully programmable in order to support, for example, the centering of the active video
window within the picture frame.
The DTG also controls the data multiplexer in the DIGMUX block. DIGMUX can be programmed to pass device input
data only on active video lines (inserting DTG-generated blanking level during blanking intervals). Alternatively, the
DTG can pass device input data also during some VBI lines (ancillary data in the input stream is passed transparently
on some VBI lines). Finally, the device can also generate its own ancillary data and insert it into the analog outputs
according to the CGMS data format for the 525P video format.
3.1.6 Clock Generator (CGEN)
The clock generator is an analog delay-locked loop (DLL) based circuit and provides a 2× clock from the CLKIN input.
The 2× clock is used by the CDRV block for 2× video interpolation. Some video formats also require a 1/2 rate clock
used for 4:2:2 to 4:4:4 conversion.
3.1.7 Clock Driver (CDRV)
The clock drive block generates all on-chip clocks. Its inputs are control signals from the digital logic, the original
CLKIN, and the 2× clock from CGEN. Outputs include a half-rate clock, full-rate clock, and a 2× full-rate clock. The
clocks are used for both optional on-chip interpolation processes: 4:2:2 to 4:4:4 interpolation and 1× to 2× video
oversampling.
3.1.8 I²C Host Interface (I2CSLAVE)
The I²C interface controls and programs the internal I²C registers. The THS8200 I²C interface implementation
supports the fast I²C specification (SCL: 400 kHz) and allows the writing and reading of registers. An auto-increment
addressing feature simplifies block register programming. The I²C interface works without a clock present on CLKIN.
3.1.9 Test Block (TST)
The test block controls all the test functions of the THS8200. In addition to manufacturing test modes, this block
contains several user test modes including a DAC internal ramp generator and a 75% SMPTE video color bar
generator.
3.1.10 D/A Converters (DAC)
THS8200 contains three DACs operating at up to 205 MSPS and with an internal resolution of 11 bits. Each DAC
contains an integrated video sync inserter. The sync(s) is (are) inserted by means of additional current source circuits
either on the green/luma (Y) channel only or on all the DAC output channels, in order to be compliant with both
consumer (EIA, sync-on-G/Y) as well as professional (SMPTE, sync-on-all) standards.
The DAC speed supports all ATSC formats, including 1080P, as well as all PC graphics (VESA) formats up to UXGA
at 75 Hz (202.5 MSPS).
3–3