THS8200 Datasheet, PDF (56/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

bits into the corresponding THS8200 registers. Care should be taken to format this data according to CGMS
semantics; the user is referred to the original standards to determine header/payload data programming. To avoid
the transmission of invalid data, the data transmitted is updated only when the CGMS register with the highest
subaddress is programmed with cgms_en active.
CGMS insertion is possible in either 1× or 2× interpolated video modes of the THS8200. While EIA-805 allows the
inserted data to change on every frame, and also allows data packets that would span multiple lines (and therefore
also multiple frames, since only 1 line/frame is used for insertion), the THS8200 does not support multiline data
insertion because it is not required for CGMS.
4.12 I²C Interface
The THS8200 contains a slave-only I²C interface on which both write and read are supported. The register map
shows which registers support read/write (R/W) and which are read-only (R). The device supports normal and fast
I²C modes (SCL up to 400 kHz). The I²C interface is also operational when no input clock is received on CLKIN.
To discriminate between write and read operations, the device is addressed at separate device addresses. There is
an automatic internal sub-address increment counter to efficiently write/read multiple bytes in the register map during
one write/read operation. Furthermore, bit1 of the I²C device address is dependent upon the setting of the I2CA pin,
as follows:
• If address-selecting pin I2CA = 0, then
– write address is 40h (0100 0000)
– read address is 41h (0100 0001)
• If address-selecting pin I2CA = 1, then
– write address is 42h (0100 0010)
– read address is 43h (0100 0011)
The I²C interface supports fast I²C, i.e., SCL up to 400 kHz.
WRITE FORMAT
S
Slave address(w)
A
Sub-address
A
Data0
A
......
DataN-1
A
P
S
Slave address(w)
A
Sub-address
Data0
DataN-1
P
Start condition
0100 0000 (0x40) if I2CA = 0, or 0100 0010 (0x42) if I2CA = 1
Acknowledge, generated by the THS8200
Sub-address of the first register to write, length: 1 byte
First byte of the data
Nth byte of the data
Stop condition
4–41