THS8200 Datasheet, PDF (63/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

REGISTER
NAME
R/W
SUB-
ADDRESS
BIT7
BIT6
BIT5
BIT4
dtg2_line_ R
cnt_msb
0x7f
dtg2_ip_fmt Reserved
dtg2_line_ R
cnt_lsb
0x80 dtg2_line_cnt(7:0)
0x81 Reserved
dtg2_cntl R/W
0x82
dtg2_fid_
de_cntl
dtg2_rgb_
mode_on
dtg2_em-
bedded_
timing
dtg2_
vsout_pol
CGMS CONTROL
cgms_cntl_ R/W
header
0x83 Reserved cgms_en cgms_header(5:0)
cgms_pay- R/W
load_msb
0x84 Reserved Reserved cgms_payload(13:8)
cgms_pay- R/W
load_lsb
0x85 cgms_payload(7:0)
misc_ppl_ R
lsb
0x86 misc_ppl(7:0)
misc_ppl_ R
lsb
0x87 misc_ppl(15:8)
misc_lpf_
R
lsb
0x88 misc_lpf(7:0)
misc_lpf_
R
msb
0x89 misc_lpf(15:8)
BIT3
dtg2_h
sout_pol
BIT2
BIT1
dtg2_line_cnt(10:8)
BIT0
dtg2_fid_
pol
dtg2_vs_
pol
dtg2_hs_
pol
5.1 Register Descriptions
Legend: Between { } are shown the name(s), subaddress(es) and bit position(s) where each register can be found in
the register map.
The default register value is shown between [ ] in binary format, and hexadecimal (h) and/or decimal (d) notation
where listed.
5.1.1 System Control (Sub-Addresses 0x02–0x03)
ver(7:0):
Device version
{version 0x02(7..0)}
[0000 0000]
The user can read this register to find out which version of THS8200 is in the system.
vesa_clk:
Clock mode selection
{chip_ctl 0x03(7)}
[0]
0 : Normal operation
1 : All clocks become identical, except for the half-rate clock, and the DLL is bypassed. This is used in VESA mode to
support a direct 205-MHz input clock. No internal 2× interpolation is available. This mode should be used for all
formats that require a >80 MSPS pixel clock because the internal DLL for 2× clock generation is specified only up to
80 MSPS.
The half-rate clock is still internally generated if needed to allow, e.g., 148-MHz 20-bit input (1080P).
5–6