THS8200 Datasheet, PDF (77/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

dtg2_embedded_timing: Video sync input source
{dtg2_cntl 0x82(5)} [0]
0 : Timing of video input bus is derived from HS, VS, and FID dedicated inputs
1 : Timing of video input bus is assumed embedded in video data using SAV/EAV code sequences.
dtg2_vsout_pol:
{dtg2_cntl 0x82(4)}
0 : Positive polarity
1 : Negative polarity
VS_OUT polarity
[1]
dtg2_hsout_pol:
{dtg2_cntl 0x82(3)}
0 : Negative polarity
1 : Positive polarity
HS_OUT polarity
[1]
dtg2_fid_pol:
{dtg2_cntl 0x82(2)}
0 : Negative polarity
1 : Positive polarity
FID polarity
[1]
dtg2_vs_pol:
{dtg2_cntl 0x82(1)}
0 : Negative polarity
1 : Positive polarity
VS_IN polarity
[1]
dtg2_hs_pol:
{dtg2_cntl 0x82(0)}
0 : Negative polarity
1 : Positive polarity
HS_IN polarity
[1]
5.1.9 CGMS Control (Sub-Addresses 0x83–0x85)
cgms_en:
CGMS enable
{cgms_cntl_header 0x83(6)} [0]
0 : No CGMS data inserted.
1 : CGMS data inserted on line 41 in SDTV mode.
cgms_header:
CGMS header
{cgms_cntl_header 0x83(5:0)} [00 0000]
CGMS header data
cgms_payload(13:0): CGMS payload
{cgms_payload_msb 0x84(5:0) and cgms_payload_lsb 0x85(7:0)}
CGMS payload data
[00 0000 0000 0000]
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