THS8200 Datasheet, PDF (71/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

dtg1_mode
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Others
MODE
ATSC mode 1080P (SMPTE 274M progressive) [HDTV]
ATSC mode 1080I (SMPTE274M interlaced) [HDTV]
ATSC mode 720P (SMPTE296M progressive) [HDTV]
Generic mode for HDTV [HDTV]
ATSC mode 480I (SDTV 525 lines interlaced) [SDTV]
ATSC mode 480P (SDTV 525 lines progressive) [SDTV]
VESA master [VESA]
VESA slave [VESA]
SDTV 625 interlaced [SDTV]
Generic mode for SDTV [SDTV]
[Null]
dtg1_frame_size(10:0): Generic mode frame size
{dtg1_frame_field_size_msb 0x39(6:4) and dtg1_framesize_lsb 0x3A(7:0)}
Determines number of lines per frame when in generic mode
[011 0000 0000]
dtg1_field_size(10:0): Generic mode field size
{dtg1_frame_field_size_msb 0x39(2:0) and dtg1_fieldsize_lsb 0x3B(7:0)} [000 0010 0000]
Determines number of lines in field 1 when in generic mode. This number should be programmed higher than
frame_size for progressive scan formats.
dtg1_vesa_cbar_size(7:0): Color bar pattern, width
{dtg1_vesa_cbar_size 0x3C(7:0)} [1000 0000]
Sets the width of each color bar in the color bar test pattern. This test pattern is only available when the DTG is in
VESA mode.
5.1.6 DAC Control (Sub-Addresses 0x3D–0x40)
dac_i2c_cntl:
DAC I²C control
{dac_cntl_msb 0x3D(6)} [0]
0 : DAC normal operation
1 : DAC inputs are fixed to values of <dac_cntl> registers.
dac1_cntl(9:0):
DAC1 input value
{dac_cntl_msb 0x3D(5:4) and dac1_cntl_lsb 0x3E(7:0)}
Direct input to G/Y DAC
[00 0000 0000]
dac2_cntl(9:0):
DAC2 input value
{dac_cntl_msb 0x3D(3:2) and dac2_cntl_lsb 0x3F(7:0)}
Direct input to B/Cb DAC
[00 0000 0000]
dac3_cntl(9:0):
DAC3 input value
{dac_cntl_msb 0x3D(1:0) and dac3_cntl_lsb 0x40(7:0)}
Direct input to R/Cr DAC
[00 0000 0000]
5–14