THS8200 Datasheet, PDF (32/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

vertical or horizontal sync is received, either from dedicated inputs or from embedded SAV/EAV codes, the output
frame starts at position (x,y). This ensures that, for example, the output video frame can be centered on the display.
Based on the 0-reference of the DTG, the line types are generated and the DIGMUX will select between the video
input and the DTG output for each line type. All horizontal timings of the different line types are programmable,
including the portion of the video line seen as active video. A complete overview of all available line types in either
SDTV or HDTV mode is presented in Section 4.7.3.
Additionally, Hsync/Vsync outputs can be generated, synchronized to the THS8200 DAC outputs. These outputs are
programmable in width, position and polarity, based on the horizontal/vertical pixel counters, and thus independently
of the DTG reference. This ensures that independent synchronization is possible between the composite sync output
inserted into the DAC output(s) and the dedicated Hsync/Vsync outputs. Because of their programmability, these
output signals could be used for other purposes as well; e.g., Vsync could be programmed as a signal active during
the VBI.
Figure 4–15 shows how the internal pixel and line counters are synchronized to internal HS and VS signals in slave
mode. HS and VS are internal signals derived from either HS_IN, VS_IN, or from embedded SAV/EAV codes in the
input video data. Since the 0-reference of the DTG is determined by these counters, the dtg2_vs_in_dly and
dtg2_hs_in_dly register settings influence both HS_OUT, VS_OUT and composite sync output timing. The
dtg2_vdly<1,2> and dtg2_hdly settings, on the other hand, only affect HS_OUT and VS_OUT, because they are
downstream of the pixel counter. Likewise, dtg2_hlength and dtg2_vlength<1,2> only affect these dedicated sync
output signals.
4–17