THS8200 Datasheet, PDF (30/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

• the I/O direction of the HS_IN and VS_IN input signals (master vs slave mode), and the polarity of the
HS_IN, VS_IN, and FID signals
– registers: dtg2_hs_pol, dtg2_vs_pol, dtg2_fid_pol
• the position and width of the HS_OUT, VS_OUT output signals, and their polarity
– registers: dtg2_hlength, dtg2_hdly, dtg2_vlength1, dtg2_vdly1, dtg2_vlength2, dtg2_vdly2,
dtg2_vsout_pol, dtg2_hsout_pol
• field reversal within DTG
– register: dtg1_field_flip
• the active video window: width and position of horizontal blanking interval, width and position of vertical
blanking interval
– registers: dtg2_bp<n>, dtg2_linetype<n> and the dtg1_spec_x registers, see DTG Line Type Overview
(Section 4.7.3).
• the composite sync format: horizontal line timing includes serration, interlaced sync and broad pulses on
each line in vertical blanking interval, width of vertical sync
– registers: dtg1_mode, dtg1_spec_<a,b,c,d,d1,e,g,h,i,k,k1>
• the behavior of the composite sync insertion: inserted on G/Y-channel only, or inserted on all channels, or
no composite sync insertion; the amplitudes of the inserted negative and positive sync, the amplitudes of
all serration pulses and broad pulses during the vertical blanking interval
– registers: dtg1_<y,cbcr>_sync_high, dtg1_<y,cbcr>_sync_low
• the DAC output amplitude during blanking and whether video data is passed or not during the active video
portion of lines within the vertical blanking interval that contain no vertical sync, serration, or broad pulses
– registers: dtg1_<y,cbcr>_blank, dtg1_pass_through
• the width of each color bar of the color bar test pattern
– registers: dtg1_vesa_cbar_size
4.7.2 Functional Description
The user should program the DTG with the correct parameters for the current video format. The DTG contains a line
and a pixel counter, and a state machine to determine which user–defined line waveform to output for each line on
the analog outputs. The pixel counter counts horizontally up to the total number of pixels per line, programmed in
‘dtg1_total_pixels’. The line counter counts up to ‘dtg1_field_size’ lines in the first field, and continues its count up
to ‘dtg1_frame_size’ lines in the total frame (field1+field2).
The current field is derived from the even/odd field ID signal, which is sampled at the start of the Vsync period. The
source for the internal FID signal can be either the signal to the FID terminal, or can be internally derived from relative
Hsync/Vsync alignment on the corresponding terminals, as selected by ‘dtg2_fid_de_cntl’ and the current DTG mode
(VESA vs. SDTV/HDTV). See register map description of ‘dtg2_fid_de_cntl’ for more details. Derivation of FID from
Hsync/Vsync input alignment is done according to the EIA–861 specification. There is a tolerance implemented on
Hsync/Vsync transition misalignment. When the active edge of the Vsync transition occurs within +/– 63 clock cycles
from the active edge of Hsync, both signals are interpreted as aligned, which signals field 1. Because of this timing
window, the internal FieldID signal is generated later than the start of Vsync period. Since the signal is internally
sampled at the start of the Vsync period to determine the current field, the field interpretation is opposite. Use the
‘field_flip’ register to correct this through field reversal.
If the video format is progressive, only field1 exists and no FID signal is needed. However the DTG will only startup
when a field 1 condition is detected i.e when FID is detected low at the start of the Vsync period. Thus in the case
of a progressive video format, and when using the device with external FID input, the user must make sure to keep
the FID terminal low.
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