THS8200 Datasheet, PDF (82/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

blanking-level amplitude outside the active video window on its analog outputs; this blanking level can be correctly
positioned for either RGB or YPbPr analog outputs. The user can optionally perform color space conversion in the
THS8200 and adjust offset and gain ranges through the device’s CSM block.
When sending (interlaced) video over DVI, the EIA-861 specification describes a method to derive the fieldID
signal—not directly available from a DVI1.0 (with HDCP) receiver—from the relative alignment of the Hsync and
Vsync signals. The THS8200 can be configured to derive internally the correct even/odd field identification from
Hsync/Vsync alignment according to this specification, instead of using the FieldID signal on its FID input terminal.
This avoids the need for additional glue logic in a DVI application.
6.3 Master vs Slave Timing Modes
In slave timing mode, the THS8200 output display timing is synchronized to the video data source. Display timing
output signals are based on input sync signals, either fed to the device on the dedicated Hsync, Vsync, and FieldID
(HS_IN, VS_IN, and FID) input terminals or based on SAV/EAV codes embedded in the input video data.
GY[9:0]
BPb[9:0]
RPr[9:0]
MPEG Decoder/
Graphics Processor/
Video Memory
CLKIN
HS
VS
FID
THS8200
G/Y
B/Pb
R/Pr
HS_OUT
VS_OUT
Drive TV or
Computer Monitor
To an I2C
Master Device
SDA
SCL
To an NTSC/PAL
Encoder
Figure 6–3. Slave Operation Mode of THS8200
In master timing mode, the THS8200 generates two sets of output synchronization signals
• HS_IN, VS_IN now become output signals to the video source (FID unused)
• HS_OUT, VS_OUT are still output signals to display device
The intended purpose is that THS8200 requests video data from a source that requires external timing, such as video
memory.
6–2