THS8200 Datasheet, PDF (75/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

LINE TYPE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
dtg1_linetype <n>(3:0)
ACTIVE_VIDEO
FULL_NTS
FULL_BTSP
NTSP_NTSP
BTSP_BTSP
NTSP_BTSP
BTSP_NTSP
ACTIVE_NEQ
NSP_ACTIVE
FULL_NSP
FULL_BSP
FULL_NEQ
NEQ_NEQ
BSP_BSP
BSP_NEQ
NEQ_BSP
dtg2_hlength(9:0):
HS_OUT duration
{dtg2_hlength_lsb_hdly_msb 0x71(7:6) and dtg2_hlength_lsb 0x70(7:0)}
Sets the duration of the HS_OUT output signal.
[00 0110 0000]
dtg2_hdly(12:0):
HS_OUT delay
{dtg2_hlength_lsb_hdly_msb 0x71(4:0) and dtg2_hdly_lsb 0x72(7:0)} [0 0000 0000 0010]
Sets the pixel value that the HS_OUT signal is asserted on. Note: when programmed to a value higher than the total
number of pixels per line, there will be no HS_OUT output.
dtg2_vlength1(9:0):
VS_OUT duration, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(7:6) and dtg2_vlength1_lsb 0x73(7:0)} [00 0000 0011]
Sets the duration of the VS_OUT output signal during progressive scan video modes or during the vertical blank
interval of field 1 in interlaced video modes.
dtg2_vdly1(10:0):
VS_OUT delay, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(2:0) and dtg2_vdly1_lsb 0x75(7:0)} [000 0000 0011]
Sets the line number that the VS_OUT signal is asserted on for progressive video modes or for field 1 of interlaced
video modes. Note: when programmed to a value higher than the total number of lines per frame, there is no
VS_OUT output.
dtg2_vlength2(9:0):
VS_OUT duration, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(7:6) and dtg2_vlength2_lsb 0x76(7:0)} [00 0000 0000]
Sets the duration of the VS_OUT output signal during the vertical blank interval of field 2 in interlaced video modes.
In progressive video modes, this register must be set to all 0.
dtg2_vdly2(10:0):
VS_OUT delay, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(2:0) and dtg2_vdly2_lsb 0x78(7:0)} [111 1111 1111]
Sets the line number that the VS_OUT signal is asserted on for field 2 of interlaced scan video modes. For
progressive scan video modes, this register must be set to all 1.
5–18