THS8200 Datasheet, PDF (13/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

3 THS8200 Functional Overview
gy_in
bcb_in
rcr_in
hs_in
vs_in
ifir
Color
dly
Space
ifir
Convertor
ifir
ifir
ifir
4:2:2 to 4:4:4
ifir12_bypass
ifir35_bypass
scl_in
scl_out
scl_en
sda_in
sda_out
sda_en
I²C
Slave
sav
Display
Timing
eav
Generator _{dtg_data}
databus_in
databus_out
address
addr_en
ready
cscouts
digbypass
Clip
Scale
dg
Multiplier
db
dr
dg_bias
db_bias
dr_bias
Three Channel DACs
dr_bias
dg_bias
db_bias
hs_out
vs_out
csmouts
ifirouts
digbypass
do[9:0]
dlclko
arst_func_n
dmanouts
tstmode
clkin
clk_h
clk_f
clk_fx2
cdrv ^2X cgen
clkin
Clock Generator
Offset Binary Signals
Figure 3–1. Functional Block Diagram
3.1 Data Manager (DMAN)
The data manager is the block that transforms the selected input video data format present on the chip input bus(es)
to an internal 10-bit three-channel representation. Supported input formats include 10/8 bit ITU-R.BT656 with
embedded sync codes, 15-/16- or 24-/30-bit RGB with external sync, 20-/16-bit SMPTE274M/296M with embedded
sync codes, as well as 20-/16-bit YCbCr 4:2:2 with external sync. The user can optionally include a 4:2:2 to 4:4:4
3–1