THS8200 Datasheet, PDF (31/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

It is also needed for proper DTG synchronization that the programmed Hsync and Vsync input polarities are correct.
Since Hsync, Vsync polarities change for different VESA PC formats, the device has built–in support to detect the
incoming sync polarities. This is done by comparing the width of Hsync high (‘misc_ppl’) to the total line length
(‘dtg2_pixel_cnt’) to derive the Hsync duty cycle and thus its polarity. Upon this detection, the user can program the
detected incoming polarity for DTG input synchronization (‘dtg2_hs_pol’) – it is not set automatically by the device.
The procedure is similar for Vsync polarity detection, using registers ‘misc_lpf’, ‘dtg2_line_cnt’ and ‘dtg2_vs_pol’.
The DTG synchronization can be separated into three functions:
• Internal synchronization: how the DTG is synchronized with respect to the internal horizontal and vertical
counters
• Source synchronization: how the horizontal and vertical counters are synchronized to the
HS_IN/VS_IN/FID or SAV/EAV signals
• Output synchronization: how the output timings HS_OUT, VS_OUT, and the composite sync output are
synchronized to the DTG and the horizontal and vertical counters
The DTG is based on a state machine that can generate a set of line types which can override the values on the DAC
inputs. The DTG output is multiplexed into the data path by the DIGMUX. The selected video format preset setting,
or the programmed (line type, breakpoint) table in case a generic mode is selected in dtg1_mode, determines which
line type is generated for a particular line, and where this DTG output is used to override the normal DAC inputs.
Internally, a fixed preconfigured number of line types exists from which the user can select.
Also, for each set of line types (we will see next there are two different sets of line types possible) the user can program
the horizontal duration of each predefined excursion (negative sync, positive sync, back porch, front porch, broad
pulse, interlaced sync, etc.) and also the amplitude (e.g., negative sync amplitude, positive sync amplitude, blank
amplitude).
The setting of dtg1_mode determines:
• Internal synchronization: the 0H reference (horizontal reset of the DTG) is different between SDTV and
HDTV.
• Output synchronization: the available set of output synchronization line types depends on these modes.
The user can choose from a number of predefined line types for each mode. In each mode, the user is able
to program the timings along the line. However some timings are hard coded by the selected DTG_mode
(e.g., rise/fall times for sync are different; see DTG Line Type Overview, Section 4.7.3) and not all line types
can be selected in each DTG mode (e.g., HDTV allows tri-level sync, while SDTV only allows generation
of bi-level negative syncs).
4.7.2.1 Predefined DTG Video Formats (presets)
While the DTG has the flexibility to generate a wide array of video output formats and their synchronization signals,
the most common video formats have predefined settings for the field and frame sizes and for (line type, breakpoint)
settings.
When selecting a video format preset, the horizontal timings of the line types still need to be programmed. The preset
only fixes the (line type, breakpoint) table.
4.7.2.2 Internal Synchronization
The pixel and line counters of the DTG are reset by internal signals. In slave mode (THS8200 slaves to external video
input source) these signals are derived from either the embedded SAV/EAV codes or the dedicated Hsync/Vsync/FID
inputs. In master mode, these counters are in free-run and the HS_IN/VS_IN signals are generated by the THS8200
based on the programmed field/frame parameters. Master mode is only available for progressive-scan VESA modes.
FID is not generated in master mode.
The user can delay, in both horizontal and vertical directions, the 0-reference of the DTG by programming the input
delay registers. Physically, the horizontal and vertical DTG startup values are altered. The effect is that, when a
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