THS8200 Datasheet, PDF (16/97 Pages) Texas Instruments – ALL FORMAT OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH THREE 11-BIT DACS,CGMS DATA INSERTION

4 Detailed Functional Description
4.1 Data Manager (DMAN)
Table 4–1. Supported Input Formats
INPUT INTERFACE
TIMING CONTROL
SYNCHRONIZATION
30-BIT
20-BIT
10-BIT(1)
16-BIT
15-BIT
EMBEDDED
TIMING
DEDICATED
TIMING
MASTER
SLAVE
[PRESET]
HDTV-SMPTE296M
X (4:4:4) X (4:2:2)
X
X
progressive (720P)
[PRESET]
HDTV-SMPTE274M
X (4:4:4) X (4:2:2)
X
X
progressive (1080P)
[PRESET]
HDTV-SMPTE274M
X (4:4:4) X (4:2:2)
X
X
progressive (1080I)
[GENERIC] HDTV
X (4:4:4) X (4:2:2)
X
X
X
[PRESET]
SDTV-ITU.1358 (525P)
X(2)
X
X
[PRESET]
SDTV-ITU-R.BT470 (525I)
X(3)
X
X
[PRESET]
SDTV-ITU-R.BT470 (625I)
X(3)
X
X
[GENERIC] SDTV
X (4:4:4) X (4:2:2)
X
X
X
[PRESET] VESA
X(4)
X(4) X(4)
X
X
X
NOTES:
1. When the device is configured to receive data over a 10-bit interface, the ITU-R.BT656 output bus on the THS8200 can be enabled
via an I2C register bit to send the received data to an external device.
In other DMAN modes, this output should remain off (data_tristate656 register).
2. SMPTE293M-compliant
3. ITU-R.BT656-compliant
4. Because PC graphics data is normally only 8 bits wide, only 3×8 bits (8 MSBs of each bus) are used. Color space converter bypass
is required for modes with pixel clock > 150 MSPS.
Table 4–1 summarizes all supported video mode configurations.
Each video mode is characterized by three attributes:
• Input Interface: Data is accepted over 10-, 20- or 30-bit interface (or 8 ,16, 24 bit interface for 8-bit data
when using 8 MSBs of each input data bus and connecting 2 LSBs to ground). This selection is controlled
by the dman_cntl register.
• Timing control: Video timing is either embedded in the data stream or supplied via dedicated timing
signals. In the latter case additional Hsync (HS_IN), Vsync (VS_IN) and FieldID (FID) input signals are
required to synchronize the video data source and THS8200 in the case of slave timing mode. This selection
is controlled by the dtg2_embedded_timing register.
• Synchronization: Video timing either is supplied to the device (slave) or the THS8200 requests video data
from the source (master). This selection is controlled by the chip_ms register.
NOTE: Device operation with combinations of settings for the dman_cntl,
dtg2_embedded_timing and chip_ms registers that result in operating modes not marked in
Table 4–1 is not assured. See detailed register map description for actual register settings.
Furthermore, Table 4–1 shows for which modes presets are defined. When in a preset video mode, the
line-type/breakpoint-pairs that define the frame format (see Display Timing Generator, Section 4.7) are
4–1